Updated Hardware Init file and more

Since last publication have been implemented:

  • Rotor Position Detection Algorithm;
  • Three motor wires integrity control;
  • 16 MHz clock now with wait states for 8 MHz FRAM;
  • PWM regulation has 256 steps for 31.250 kHz or 512 steps for 15.625 kHz;

Start an implementation of Fuzzy Logic speed regulator (closed loop).

Hardware Init file has now initialization almost all parts of BLDC controller:

  • Clock 16 MHz;
  • LFXT 32kHz crystal pins initialization;
  • Real Time Clock;
  • pins: GPIO, six output PWM, five inputs ADC12 and input for capture TA1;
  • eUSCI as full duplex UART interface configured for 460800 bps;
  • 31.25 kHz PWM timer TB0 with 256 steps of control;
  • TA0 for six phase switching;
  • TA1 for “standard” external speed control (1…2 ms PWM);
  • ADC12 5 channels: 3 – BEMF and 2 – voltage and current;
  • DMA for UART communication;